Everyone looks good
on paper now.
Who can actually
do the job?

Role and environment

Senior FPGA Engineer for an RF product team using VHDL, Xilinx devices and embedded C.

Technical ownership

RTL design, simulation, timing closure, high-speed interfaces, hardware debugging and firmware integration.

Candidate-reported evidence

Reports ownership of VHDL modules for an RF signal-processing product and taking designs through synthesis and timing analysis.

Supporting evidence

Employment history consistently references FPGA development, laboratory debugging and work with RF and firmware engineers.

Gaps and uncertainties

Exact clock rates, timing constraints and ownership of the verification strategy need clarification. No code or design artefacts have been independently inspected.

Technical interview questions

1. Describe an RTL block you owned from specification through hardware validation.
2. What caused your most difficult timing failure, and how did you isolate it?
3. Which faults appeared only after FPGA, RF hardware and firmware were integrated?

Candidate-reported experience is identified as such. RunTime organises the available evidence and identifies questions for further investigation.